The present invention relates generally to power supplies, and more particularly, is directed to a more efficient switch mode power supply.
Linear power supplies have conventionally been provided for various circuits. However, such linear power supplies are generally not very efficient, and are also relatively large. For this reason, switch mode power supplies are preferred in many instances, due to the fact that they dissipate much less heat and require less cooling than linear power supplies, because they are much more efficient. Further, switch mode power supplies require less surface area for cooling than linear power supplies, thereby reducing the size. However, the efficiency of such switch mode power supplies is still not entirely satisfactory, and there is much wasted energy.
Conventionally, such switch mode power supplies have used passive diodes. A primary winding at the input and a secondary winding at the output are provided, along with passive diodes in the output circuit following the secondary winding. Specifically, such a power supply includes a primary winding and a secondary winding, with the primary winding being driven through a circuit of MOSFETs and diodes, by means of drive pulses which are pulse width modulated (PWM) pulses. From the secondary winding, the output is derived through passive diodes and a choke coil. The problem with this circuit is that there is a large forward voltage drop across the passive diodes at the output, which dissipates much power, making the power supply inefficient. Examples of such circuits are disclosed in U.S. Pat. Nos. 5,781,420 and 6,061,255.
For this reason, it is known to replace the passive diodes at the output of the secondary winding with actively controlled switches, such as MOSFETs, which can be turned on and off with a voltage control signal. The forward voltage drop across the MOSFETs is much smaller than that across the passive diodes, so as to dissipate less power and thereby greatly increase the power efficiency of the circuit. The actively controlled switches are commonly referred to as "synchronous rectifiers."
The actively controlled switches only permit current flow when they are activated. Thus, the activating signals must have the correct timing relationship to other activities in the circuit for maximum efficiency, that is, the actively controlled switches must be synchronized with other circuit elements.
However, with such known circuits, the circuitry for turning the MOSFETs on and off at the output of the secondary winding is very complicated and not entirely accurate. Specifically, the signals supplied to the inputs of the MOSFETs for turning them on and off are derived from the output of the secondary winding. In order to do this, it is necessary to use delay circuits, and this is not an easy task. Specifically, the delay circuits are provided since it is necessary to turn off one MOSFET before the other MOSFET turns on. It is very difficult, however, to control the delay times with the delay circuits.
Also, the delay times are dependent upon frequency changes. Therefore, if there is a frequency change in the system, all delay times must be changed. Further, if there is a frequency variation in the circuit, all of the timings will be off, which could render the circuit inoperable.
An example of such a circuit is shown in U.S. Pat. No. 5,726,869. In this circuit, the output from pulse width modulator (PWM) 5 is used to turn off FET Q5 at the same time that FET Q1 turns off. However, it is required, for the circuit to be operative, that FET Q1 must turn on after FET Q5 turns off. Accordingly, this circuit must use an inherent delay which is insufficient. Specifically, assuming a sawtooth waveform, this circuit turns the FETs on and off at the lower level of the waveform, which is used to control the PWM signal. However, a delay circuit is needed to accomplish this result. The same applies to the circuit of U.S. Pat. No. 4,870,555, which requires the use of gate delays to turn off one FET before the other FET is turned on. See also U.S. Pat. No. 6,069,802 which provides an inherent time delay circuit.
U.S. Pat. No. 5,999,420 is another example that uses time delays, and specifically provides a time delay circuit 8 for this purpose. The same applies with the delay circuits 113-115 of U.S. Pat. No. 5,742,491. Other circuits of interest are disclosed in U.S. Pat. Nos. 5,519,599; 5,708,571; 5,862,043; 5,781,420; and 6,061,255, each of which controls the FETs by an output from the secondary winding, and each of which therefore requires circuitry that provides a time delay.